The present invention relates to a phase-locked loop circuit and, more particularly, to a phase-locked loop circuit with an I-path and a P-path, and a method thereof.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional phase-locked loop circuit 100 with a proportional path (P-path) and an integral path (I-path). The phase-locked loop circuit 100 includes a phase/frequency detector 102, a first charge-pump circuit 104, a voltage-controlled oscillator (VCO) 106, a second charge-pump circuit 108, an integrator 110, and a frequency divider 112. The phase/frequency detector 102 detects a phase difference between a reference clock signal Sref and a feedback clock signal Sf to generate a phase error signal Se. The first charge-pump circuit 104 generates a proportional signal Sp for the voltage-controlled oscillator 106 according to the phase error signal Se while the second charge-pump circuit 108 generates an integral signal Si for the voltage-controlled oscillator 106. The voltage-controlled oscillator 106 generates an oscillating signal So according to the proportional signal Sp and the integral signal Si outputted by the integrator 110. Then, the frequency divider 112 divides the frequency of the oscillating signal So by N to generate the feedback clock signal Sf. The phase/frequency detector 102 and the first charge-pump circuit 104 comprise the P-path while the phase/frequency detector 102, the second charge-pump circuit 108, and the integrator 110 comprise the I-path of the phase-locked loop circuit 100. In addition, the open loop transfer function Topen of the phase-locked loop circuit 100 is expressed as equation (1):
                              T          open                =                              (                                          K                p                            +                                                K                  i                                                  s                  ·                  C                                                      )                    ·                                    K              vco                                      N              ·              s                                                          (        1        )            wherein Kp is the gain of the P-path and
      K    i        s    ·    C  is the gain of the I-path, Ki is the gain of the phase/frequency detector 102 in conjunction with the second charge-pump circuit 108, C is the capacitance of the capacitor in the integrator 110, and s is the so-called s parameter.
One of the main features of the configuration of the phase-locked loop circuit 100 is to save resistors in the loop filter, wherein the resistors would occupy a large area of the total area of the phase-locked loop circuit 100, thereby increasing the cost of the phase-locked loop circuit 100. In the conventional phase-locked loop circuit 100, however, the capacitor in the integrator 110 may still occupy a considerable area of the total area. Since the large occupied area means a correspondingly high cost, how to effectively reduce the total area of the phase-locked loop circuit 100 is an urgent problem in this field.